Computer Architecture, 3D stacking, Mobiquitous Computing
Ph.D. in Electrical Engineering and Computer Science, 2001, University of Michigan.
Murali Annavaram is an Associate Professor in the Ming Hsieh Department of Electrical Engineering at USC. Prior to his appointment at USC he was a visiting research faculty at Nokia Research Center Palo Alto. His research at Nokia focused on exploring features required for mobile devices in order to provide location and context-aware computing services. Prior to Nokia he was a senior research scientist at Intel Microprocessor Research Labs where his research spanned the entire spectrum of systems architecture ranging from high level software issues to low level device variations. His research at Intel focused on a wide range of topics: 3D stacking, EPI throttling for power efficient CMP designs, impact of process variability on chip designs, characterizing server workloads for improving simulation and tracing technologies. Murali received his PhD from University of Michigan in 2001 focusing on prefetching techniques for irregular application. Murali enjoys hiking, running, and best of all traveling around the world with his wife and three year old handful!
The decade of 80s has been hailed as the era of supercomputing in a room. 90s is the era of supercomputing on a desktop and finally the current decade is the era of supercomputing on a laptop. The dramatic reduction in computer form factor is a cumulative result of innovations at all levels of computer design; from process technologies to architectural innovations. There are, however, signs that the rate of process technology scaling is slowing and process variations are becoming dominant while at the same time architectural innovations are facing stringent constraints on power consumption. I consider these challenges as new research opportunities. Hence, my research will focus on bringing the power of supercomputing into a pocket within the next decade. In order to achieve this goal extreme system integration is the key first step. Based on my industrial research experience I plan to pursue 3D stacking as the technology enabler for such system integration. In particular, I will explore the challenges and opportunities in stacking heterogeneous system components such as graphics, network processors, flash memory and even I/O components such as solid state disk drives in a single 3D stack. 3D stacking allows disparate silicon technologies to be combined in a die stack, while dramatically reducing the latency between components.These advantages open up new design tradeoffs that were infeasible earlier. For instance, stacking memory on GPU can reduce the need for expensive GDDR memory since 3D DRAM exceeds the bandwidth capabilities of GDDR. My current research on 3D stacking gave me insights into the power, performance, thermal and design issues for 3D stacking. I plan to use some of these insights to expand my research agenda to explore more aggressive 3D stacking options.
Once the power of supercomputing is available in a users pocket the logical next step is to harness the collective compute and communication power of billions of mobile devices to create new usage models in future, such as real time traffic monitoring and social networking. I will research how to allow mobile devices to proactively interact and share the knowledge of their surroundings without compromising privacy and security. For instance, a mobile device user can request for a recommendation of a restaurant with the least waiting times within the vicinity. Users in nearby restaurants can provide this information in real time, provided the information does not compromise the privacy and the provider has an incentive for providing the information. There are challenges both at the hardware and software level for these new usage models to work, which will be the focus of my mobile platform research.