lfsr Project Status | |||
Project File: | lfsr.xise | Parser Errors: | |
Module Name: | lfsr | Implementation State: | Synthesized |
Target Device: | xc6slx16-3csg324 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 17 | 4656 | 0% | |
Number of Slice Flip Flops | 12 | 9312 | 0% | |
Number of 4 input LUTs | 33 | 9312 | 0% | |
Number of bonded IOBs | 33 | 232 | 14% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Sep 21 16:16:32 2016 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu Sep 22 07:43:09 2016 |