lfsr Project Status
Project File: lfsr.xise Parser Errors:
Module Name: lfsr Implementation State: Synthesized
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 17 4656 0%
Number of Slice Flip Flops 12 9312 0%
Number of 4 input LUTs 33 9312 0%
Number of bonded IOBs 33 232 14%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Sep 21 16:16:32 2016000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Sep 22 07:43:09 2016

Date Generated: 02/14/2017 - 15:10:11