

Journals, Articles & Patents
 The BorelTanner distribution, Biometrika, vol. 47, pp. 143150, 1960, with F.A. Height.
 A multiplyadd operation for a serial digital computer, U.S. Patent, ThompsonRamoWoolridge Corporation (1961), with L. Amdahl and J. Davis.
 The minimization of Boolean functions containing unequal and nonlinear cost functions, ACM 1962 Conference Digest, September 7, 1962, Syracuse, New York.
 Techniques for simulation of computer logic, Comm. of the ACM, pp. 443446, July 1964.
 Digitalization of continuous control systems, Simulation, vol. 5, no. 5, pp. 329337, November 1965.
 Implementation of threshold nets by integer linear programming, IEEE Trans. on Electronic Computers, vol. EC14, no. 6, pp. 950952, December 1965.
 The formulation of some allocation and connection problems as integer programs, Naval Research Logistics Quarterly, vol. 13, no. 1, pp. 8395, March 1966.
 Coding the vertices of a graph, IEEE Trans. on Information Theory, vol. IT13, no. 2, pp. 148153, April 1966.
 The application of integer programming in design automation, Proc. SHARE Design Automation Workshop, May 1966.
 General survey of design automation of digital computers, Proc. of the IEEE, vol. 54, no. 12, pp. 17081721, December 1966.
 Adaptive computers, Information Control, vol. 11, no. 4, pp. 402422, October 1967.
 An unexpected result in coding the vertices of a graph, Journal of Mathematical Analysis and Applications, vol. 21, no. 3, pp. 583600, December 1967, with J. Folkman.
 Some properties of (0,1) circulant matrices, Proc. of the Hawaii Int’l Conference on System Sciences, pp. 793794, January 1968.
 Heuristic switching expression simplification, Proc. 23^{rd} National Conference of the ACM, pp. 241250, 1968.
 Fault detection in linear cascades of identical sequential machines, Proc. IEEE Conf. on Switching and Automata Theory, pp. 235244, 1968.
 Hardware fault detection, Proc. Fall Joint Computer Conference, vol. 33, pp. 15011503, 1968.
 Combinational equivalences of (0,1) circulant matrices, Journal of Computer and System Science, vol. 3, no. 1, pp. 828, February 1969.
 Generation of optimal code for expressions via factorization, Comm. of the ACM, vol. 12, no. 6, pp. 333340, June 1969.
 Logic synthesis, Proc. Joint Conf. on Mathematical and Computer Aids to Design, pp. 146161, October 1969, IEEE Catalogue No. 69C 63C.
 Simplification of the covering problem with applications to Boolean expression, JACM, vol. 17, pp. 166182, January 1970.
 Functional partitioning and simulation of digital circuits, IEEE Trans. on Computers, vol. C19, pp. 10381046, November 1970.
 Generation of fault detection tests for sequential circuits, Digest Int’l Symposium on FaultTolerant Computing, pp. 1821, March 13, 1971.
 An algorithm for generating a fault detection test for a class of sequential circuits, presented at the Int’l Symposium on the Theory of Machines and Computations, August 1971, Haifa, Israel; republished in Theory of Machines and Computations, Z. Kohavi (ed.), Academic Press, pp. 313326, 1971.
 A random and an algorithmic technique for fault detection test generation for sequential circuits, IEEE Trans. on Computers, vol. C20, pp. 13641371, November 1971.
 Generation of fault tests for linear logic networks, IEEE Trans. on Computers, vol. C21, pp. 7983, January 1972.
 Recent developments in the automated design and analysis of digital systems, Proc. of the IEEE, vol. 60, pp. 1227, January 1972.
 A note on threevalued logic simulation, IEEE Trans. on Computers, vol. C21, pp. 399402, April 1972.
 Recent developments in design automation, Computer, pp. 2335, May/June 1972.
 Generation of fault detection tests for intermittent faults in sequential machines, Digest Int’l Symposium on FaultTolerant Computing, pp. 5357, June 1972.
 Automatic test generation for sequential and combinational logic, Proc. of the National Electronic Packaging Conference (NEPCON), pp. 109117, 1972, Anaheim, California.
 Automatic test generation for digital networkssome experimental results, Digest Computer Simulation Conference, pp. 98108, June 1972, San Diego, California, with S.Y.H. Su.
 Testing for intermittent faults in digital computers, IEEE Trans. on Computers, vol. C22, pp. 241245, March 1973.
 The smallest manyvalued logic for the treatment of complemented error signals, 1973 Int’l Symposium on MultipleValued Logic, pp. 2937, May 2425, 1973, Toronto, Canada, with G. Epstein.
 Analysis of the detectability of faults by random test patterns in a special class of NAND networks, Comput. and Elect. Engineering, vol. 1, pp. 171186, 1973, with H. Huang.
 Initial design concepts for an advanced design automation system, Proc. 11^{th} Design Automation Workshop, pp. 366371, June 1719, 1974, with A.D. Friedman.
 Modeling circuits for test generation, Proc. Int’l. Symposium on FaultTolerant Computing, pp. 313 to 318, June 1974.
 Procedures for eliminating static and dynamic hazards in test generation, IEEE Trans. on Computers, vol. C23, pp. 10781092, October 1974.
 The effects of races, delays, and delay faults on test generation, IEEE Trans. on Computers, vol. C23, pp. 10781092, October 1974.
 Curriculum on design automation at the University of Southern California, Proc. ACM National Conference, November 1113, 1974.
 Why we need hardware descriptive languages, Computer, p. 19, December 1974, with J. Hayes.
 Identification of multiple stucktype faults in combinational networks, IEEE Trans. on Computers, vol. C25, no. 1, pp. 4454, January 1976, with S.J. Chang and S.Y.H. Su.
 Incremental processing in design automation, SIGDA Newsletter, vol. 6, pp. 29, November 1976.
 The smallest manyvalued logic for the treatment of complemented and uncomplemented error signals, in Computer Science and MultipleValued Logic: Theory and Applications (D.C. Rine, editor), pp. 4551, NorthHolland Publishing Company, 1977, with G. Epstein.
 Concurrent fault simulation and functional level modeling, Proc. 14^{th} Design Automation Conf., pp. 128137, June 1977, with M. Abramovici and K. Kumar.
 Some theoretical aspects of algorithmic routing, Proc. 14^{th} Design Automation Conf., pp. 2331, June 1977, with P. Agrawal.
 Generation of tests for digital circuits using generalized fault lists, Proc. 7^{th} Int’l Conference on FaultTolerant Computing, pp. 103108, June 1977, with Y. Levendel.
 A class of mincut placement algorithms, Proc. 14^{th} Design Automation Conf., pp. 284290, June 1977. Also published in 25 Years of Electronic Design Automation, by the Association for Computing Machinery, New York, NY, pp. 142148, 1988.
 The design of selfchecking multioutput combinational circuits, Proc. National Computer Conf., pp. 711721, 1977, with D.C. Ko.
 Mincut placement, Journal Design Automation and Fault Tolerant Computing, vol. 1, pp. 343362, October 1977. Also republished in VLSI Circuit Layout: Theory and Design, edited by T.C. Hu and E.S. Khu, IEEE Press, pp. 105114, 1985.
 Selfchecking of multioutput combinational circuits using extended parity techniques, Journal Design Automation and Fault Tolerant Computing, vol. 2, pp. 2962, January 1978, with D.C. Ko.
 Vector representation of switching and three valued functions, Proc. 8^{th} Annual Symp. on MultiValued Logic, May 1978, with Y. Levendel.
 Mathematical properties of Boolean transforms, Proc. 8^{th} Annual Symp. on MultiValued Logic, May 1978, with Y. Levendel.
 New concepts in automated testing of digital circuits, Proc. Symp. on Computer Aided Design of Digital Electronic Circuits, November 2729, 1978, Brussels, Belgium.
 Experiments with a density router, IEEE Trans. on Computers, vol. C28, pp. 262267, March 1979, with P. Agrawal.
 Incremental processing applied to Steinberg’s placement procedure, Proc. Design Automation Conf., pp. 2631, June 1979, with H.W. Carter and Z.A. Syed.
 Deduction of internal signal values in combinational networks based upon test results, Proc. 9^{th} Int’l. Symp. on Fault Tolerant Computing, pp. 129133, June 1979, with M. Abramovici.
 A forced directed component placement procedure for printed circuit boards, IEEE Trans. on Circuits and Systems, vol. CAS26, pp. 377388, June 1979, with N.R. Quinn, Jr.
 TEST/80a proposal for an advanced automatic test generation system, AUTOTESTCON ’79, pp. 305312, September 1979, with A.D. Friedman.
 On redundancy and fault detection in sequential circuits, IEEE Trans. on Computers, vol. C28, pp. 864865, November 1979, with M. Abramovici.
 A probabilistic model for the analysis of the routing process for circuits, Networks, vol. 10, pp. 111127, 1980, with P. Agrawal.
 Functional level primitives in test generation, IEEE Trans. on Computers, vol. C29, pp. 223235, March 1980, with A.D. Friedman.
 Fault diagnosis based on effectcause analysis: an introduction, Proc. Design Automation Conf., pp. 6976, June 1980 with M. Abramovici.
 Multiple fault diagnosis in combinational circuits based on an effectcause analysis, IEEE Trans. on Computers, vol. C29, pp. 451460, June 1980, with M. Abramovici.
 Routing of undirectional point configurations with optimal solutions for minimum wire length, congestion, and perturbation, Proc. IEEE Int’l. Conf. on Circuits and Computers, pp. 286289, October 1980, with H.W. Carter.
 Fault diagnosis in sequential circuits based upon an effectcause analysis, Digest 10^{th} Int’l. Symp. on FaultTolerant Computing, pp. 313318, October 1980, with M. Abramovici.
 A hardware router, J. Digital Systems, vol. 4, pp. 393408, Winter 1980, with K. Shamsa.
 Digital systems simulation: Current status and future trends, Proc. 18^{th} Design Automation Conference, pp. 269275, June 1981, with A. Parker.
 Probabilistic aspects of Boolean switching functions via a new transform, JACM, vol. 28, pp. 502520, July 1981, with S.K. Kumar.
 A survey of the state of the art of design automation, Computer, vol. 14, pp. 5875, October 1981, with A. Friedman and A. Iosupovicz.
 A fault collapsing analysis in sequential logic networks, BSTJ, vol. 60, no. 9, pp. 22592271, November 1981, with SJ Chang.
 A survey of the stateoftheart of design automation, Proc. 19^{th} Design Automation Conf., page 1, June 1982.
 On routing for custom integrated circuits, Proc. 19^{th} Design Automation Conf., pp. 887893, June 1982, with Z. Syed and A. El Gamal.
 Optimum placement of two rectangular blocks, Proc. 19^{th} Design Automation Conf., pp. 879886, June 1982, with M.S. Chandrasekhar.
 Bounds on channel width and a routing algorithm for a classical channel configuration, Proc. IEEE Int’l Conference on Circuits and Computers, pp. 250255, September 1982, with M.S. Chandrasekhar.
 VLSI routing, in Hardware and Software Concepts in VLSI, G. Rabbat (editor), Van Nostrand, Chapter 15, pp. 368405, 1983, with H.W. Carter.
 Fault diagnosis in sequential circuits based upon an effectcause analysis, IEEE Trans. on Computers, vol. C31, pp. 11651172, December 1982, with M. Abramovici.
 Test generation models for busses and tristate drivers, Proc. IEEE ATPG Workshop, pp. 5358, March 1983, San Francisco, California.
 The automatic design of testable circuits, Proc. IEEE ATPG Workshop, pp. 36, March 1983, San Francisco, California.
 Rowcolumn synthesis of VLSI macrocells, in Proc. IEEE Int’l Symp. on Circuits and Systems, vol. 3, pp. 12201224, May 1983, with D.W. Knapp.
 A module interchange placement machine, Proc. 20^{th} Design Automation Conference, pp. 171174, June 1983, with A. Iosupovicz and C. King.
 A placement algorithm for array processors, Proc. 20^{th} Design Automation Conf., pp. 182188, June 1983, with DJ Chyan.
 Roving emulation as a fault detection mechanism, Digest of Papers 13^{th} Int’l Symp. on FaultTolerant Computing, pp. 206215, June 1983, with A. Ismaeel.
 A methodology for custom VLSI layout, IEEE Trans. on Circuits and Systems, vol. CAS30, pp. 358364, June 1983; also in IEEE Trans. on Automatic Control, vol. AC28, pp. 671677, June 1983; also in IEEE Trans. on Systems, Man and Cybernetics, vol. SMC13, July/August 1983, with A. Kumar. (This was a special issue published by three IEEE technical societies).
 Efficient single layer routing along a line of points, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. CAD2, pp. 259266, October 1983, with H. Carter.
 Automatic design for testability based upon a cost measure, Proc. AUTOTESTCON, pp. 130143, November 1983.
 On area and yield considerations for faulttolerant VLSI processor arrays, IEEE Trans. on Computers, vol. C33, pp. 2127, January 1984, with I. Koren.
 An optimal testing algorithm for symmetric coherent systems, Journal of Mathematical Analysis and Applications, vol. 101, no. 1, pp. 170194, June 1984, with S. Salloum.
 Automatic design for testability via testability measures, IEEE Trans. on ComputerAided Design of Integrated Circuits, vol. CAD4, pp. 311, January 1985, with TH Chen.
 Incremental processing applied to Munkre’s algorithm and its application in Steinberg’s procedure, SIAM J. on Algebraic and Discrete Methods, vol. 6, no. 2, pp. 210219, April 1985, with H.W. Carter and Z.A. Syed.
 A knowledge based system for selecting a test methodology for a PLA, Proc. 22^{nd} Design Automation Conf., pp. 259265, June 1985, with XA Zhu.
 The construction of minimal area power and ground nets for VLSI circuits, Proc. 22^{nd} Design Automation Conf., pp. 794797, June 1985, with S. Chowdhury.
 Constructing optimal test schedules for VLSI circuits having builtin test hardware, Digest 15^{th} Int’l. Symposium on FaultTolerant Computing, pp. 165170, June 1985, with M. Abadir.
 A knowledge based system for designing testable VLSI chips, IEEE Design and Test of Computers, vol. 2, no. 4, pp. 5668, August 1985, with M. Abadir.
 A methodology for the design of testable VLSI chips, Proc. IEEE Workshop on Simulation and Test Generation Environments, pp. 738, Sept. 1718, 1985.
 Test schedules for VLSI circuits, IEEE Trans. on Computers, vol. C35, pp. 361367, April 1986, with M. Abadir.
 Minimal area sizing of power and ground nets for VLSI circuits, Proc. of the Fourth MIT Conf. on Very Large Scale Integration, MIT Press, C. Leiserson (editor), pp. 141169, April 79, 1986, with S. Chowdhury.
 Scan path with look ahead shifting, Proc. Int’l. Test Conf., pp. 699704, September 1986, with M. Abadir.
 Roving emulation as a fault detection mechanism, IEEE Trans. on Computers, vol. C35, no. 11, pp. 933939, November 1986, with A. Ismaeel.
 A knowledge based TDM selection system, Proc. Fall Joint Computer Conf. (FJCC), pp. 854863, November 1986, with X.A. Zhu.
 A roving emulator, Proc. 18^{th} Annual Pittsburgh Conf. on Modeling and Simulation, University of Pittsburgh School of Engineering, pp. 17451749, April 2324, 1987, with F. Cohen.
 Builtin test for folded programmable logic arrays, Microprocessors and Microsystems, vol. 11, no. 6, pp. 319329, July/August 1987, with F. Saheban.
 Analysis of BIST techniques for CMOS stuckopen faults, Proc. Int’l Workshop on Designing for Yield, University of Oxford, July 13, 1987, with S. Sastry. Republished in Yield Modeling and Defect Tolerance in VLSI, edited by W. Moore et al., Adam Hilger, Publ., Bristol and Philadelphia, pp. 249259, 1988.
 Test schedules for VLSI circuits having builtin test hardware, Int’l. Journal of Computers and Mathematics with Applications, vol. 13, no. 56, pp. 519536, 1987, with M. Abadir.
 An O(n) algorithm for width determination of power/ground routes for VLSI circuits, Integration, The VLSI Journal, vol. 4, pp. 345355, 1986, with S. Chowdhury.
 Minimal area design of power/ground nets having graph topologies, IEEE Trans. on Circuits and Systems, vol. CAS34, no. 12, pp. 14411451, December 1987, with S. Chowdhury.
 Fault tolerance in linear systolic arrays using time redundancy, Proc. 21^{st} Annual Hawaii Int’l Conf. on System Sciences, vol. I, pp. 311320, January 58, 1988, with A. Majumdar and C.S. Raghavendra.
 Optimization algorithms for a class of nonlinear programming problems, Int’l. Journal of Computers and Mathematics with Applications, vol. 14, no. 3, pp. 175 184, 1988, with S. Chowdhury.
 An objectoriented CAD database for VLSI circuits, Proc. of Vbase User’s Group Meeting and Workshop on Object Oriented Databases, May 1011, 1988, and publ. by Ontologic Inc., 47 Manning, Billerical MA, with W. Cheng, R. Gupta, I. Hardonag, E. Horowitz and S.Y. Lin.
 Optimal design of IC power/ground nets subject to reliability constraints, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 7, no. 7, pp. 787796, July 1988, with S. Chowdhury.
 A knowledge based selection system, presented at the Int’l Conf. on Applications of Artificial Intelligence in Engineering (AIENG), August 1988, and publ. in Artificial Intelligence in Engineering: Robotics and Processes, J.S. Gero, editor, Elsevier Press, pp. 237295, 1988, with X.A. Zhu.
 Analysis of testable PLA designs, IEEE Design and Test of Computers, vol. 5, no. 4, pp. 1428, August 1988, with X.A. Zhu.
 Detectability of CMOS stuckopen faults using random and pseudorandom test sequences, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 7, no. 9, pp. 933946, September 1988, with S. Sastry.
 AI Aspects of TEST: A system for designing testable VLSI chips, Proc. IFIP Workshop on Knowledge Based Systems for Test and Diagnosis, Grenoble, France, pp. 2975, September 2729, 1988, with Rajesh Gupta and Rajiv Gupta; and republished in Knowledge based systems for test and diagnosis, G. Saucier, A. Ambler and M.A. Breuer, editors, Elsevier Science Pub., North Holland Press 1989, pp. 3176.
 Knowledge based systems for test and diagnosis, Proc. IFIP Workshop on Knowledge Based Systems for Test and Diagnosis, Grenoble, France, pp. 428, September 2729, 1988, with Rajesh Gupta, Rajiv Gupta, K.J. Lee and J.C. Lien; and republished in Knowledge based systems for test and diagnosis, G. Saucier, A. Ambler and M.A. Breuer editors, Elsevier Science Pub., North Holland Press 1989, pp. 3176.
 Concurrent control of multiple BIT structures, Proc. Int’l Test Conf., pp. 431442, September 1988, with R. Gupta and J.C. Lien.
 A test and maintenance controller for a module containing testable chips, Proc. Int’l Test Conf., pp. 502513, September 1988, with J.C. Lien.
 A knowledgebased system for selecting test methodologies, IEEE Design and Test of Computers, vol. 5, no. 5, pp. 4159, October 1988, with X.A. Zhu.
 A methodology for the design of hierarchically testable and maintainable digital systems, Proc. 8^{th} Digital Avionics Systems Conference (DASC), pp. 4047, October 1720, 1988, San Jose, CA, with J.C. Lien.
 The POTATO chip architecture: A study in tradeoffs for signal processing chip design, Proc. IEEE Int’l Conf. on Computer Design (ICCD), pp. 508513, October, 1988, with R. Jain, A.C. Parker, C. Raghavendra, B. Sharma and C.Y. Tseng.
 Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor, Proc. IEEE Int’l Conf. on Computer Design (ICCD), pp. 514519, October 1988, with A. Majumdar and C.S. Raghavendra.
 Cbase 1.0: A CAD database for VLSI circuits using object oriented technology, Proc. IEEE Int’l Conf. on Computer Aided Design (ICCAD), pp. 392395, November 1988, with W. Cheng, R. Gupta, I. Hardonag, E. Horowitz and S.Y. Lin.
 Test aspects of the JPL Viterbi decoder, The Telecommunications and Data Acquisition Progress Report 4296, OctoberDecember 1988, E.C. Pasner ed., JPL, pp. 5979, February 5, 1989.
 Optimal routing of two rectangular blocks, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 8, pp. 413430, April 1989, with M. Chandrasekhar.
 An objectoriented VLSI CAD framework: A case study in rapid prototyping, Computer, vol. 22, no. 5, pp. 2837, May 1989, with W.H. Cheng, Rajiv Gupta, Rajesh Gupta, and I. Hardonag. Reprinted in ObjectOriented Databases, edited by E. Nahouraii and F. Petry, IEEE Computer Society Press, Los Alamitos, CA, pp. 4150, 1991.
 A universal test and maintenance controller for modules and boards, IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 231240, May 1989, with J.C. Lien. Reprinted in The test access port and boundaryscan architecture, C. Maunder and R. Tulloss, IEEE Computer Society Press, pp. 279288, 1990.
 BALLAST: A methodology for partial scan design, Proc. Int’l. Symp. on FaultTolerant Computing, pp. 118125, June 1989, with Rajesh Gupta and Rajiv Gupta.
 An efficient implementation of the BALLAST partial scan architecture, IFIP Int’l. Conf. on Very Large Scale Integration (VLSI 89), pp. 133142, August 1618, 1989, with Rajesh Gupta and Rajiv Gupta.
 Fault tolerance in linear systolic arrays using time redundancy, IEEE Trans. on Computers, vol. 39, no. 2, pp. 269276, February 1990, with A. Majumdar and C.S. Raghavendra.
 The BALLAST methodology of structured partial scan design, IEEE Trans. on Computers, vol. 39, no. 4, pp. 538544, April 1990, with R. Gupta.
 An extensible user interface for an objectoriented VLSI CAD framework, Proc. First Int’l Conf. on Systems Integration, Morristown, NJ., pp. 559567, April 2326, 1990, with Rajiv Gupta.
 A universal test sequence for CMOS scan registers, Proc. Custom Integrated Circuits Conf., May 1990, pp. 28.5.128.5.4, with K.J. Lee.
 On detecting single and multiple bridging faults in CMOS circuits using the current supply monitoring method, Proc. Int’l. Symp. on Circuits and Systems, pp. 58, May 1990, with K.J. Lee.
 Obstacles and an approach towards concurrent engineering, Proc. Int’l. Test Conf., pp. 260261, September 1990.
 On the charge sharing problem in CMOS stuckopen fault testing, Proc. Int’l. Test Conf., pp. 417426, September 1990, with K.J. Lee.
 SIESTA – Advanced serial scan design for testability, Proc. TECHCON ’90 (Semiconductor Research Corp.), pp. 403406, October 1990, with Rajesh Gupta.
 A new method for assigning signal flow directions to MOS transistors, Proc. Int’l. Conf. on Computer Aided Design, (ICCAD), pp. 492495, November 1990, with K.J. Lee and Rajiv Gupta.
 Applications of AI in TEST – A system for designing testable VLSI circuits, Int’l. Journal of Computer Aided VLSI Design, vol. 3, no. 2, pp. 137171, 1991, with Rajesh Gupta and Rajiv Gupta.
 Maximal diagnosis for wiring networks, Proc. Int’l. Test Conf., pp. 96105, 1991, with J.C. Lien.
 The development of a framework for VLSI CAD, in ObjectOriented Databases with Applications to CASE, Networks, and VLSI CAD, edited by Rajiv Gupta and Ellis Horowitz, Prentice Hall, pp. 237260, 1991, with Rajiv Gupta, Rajesh Gupta, W. Cheng, I. Hardonag, S.P. Lin, E. Horowitz.
 Partitioning and reorganization of hierarchical circuits for DFT, Proc. Int’l. Symp. on VLSI Design, New Delhi, pp. 106111, January 1991, with Rajiv Gupta and R. Srinivasan.
 The probability of error detection in sequential circuits using random test vectors, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 1, no. 4, pp. 245256, January 1991, with A. Ismaeel.
 An optimal scheduling algorithm for testing board interconnect using boundary scan, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 2, no. 1, pp. 117130, March 1991, with J.C. Lien.
 A partitioning method for achieving maximal test concurrency in pseudoexhaustive testing, Proc. VLSI Test Symp., pp. 3439, April 1991, with R. Srinivasan and C.A. Njinda.
 Constraints for using IDDQ testing to detect CMOS bridging faults, Proc. VLSI Test Symposium, pp. 303308, April 1991, with K.J. Lee.
 On applying circular selftest path (CSTP) technique to circuits, Proc. Custom Integrated Circuits Conf., pp. 17.7.117.7.4, May 1991, with C.A. Njinda and R. Srinivasan.
 A selfadaptive expert selection systems (SAESS) and its application to selection problems, Proc. 3^{rd} Int’l. Conf. on Software Engineering and Knowledge Engineering, pp. 116121, June 2729, 1991, with S.P. Lin and C.A. Njinda.
 Reorganizing circuits to aid testability, IEEE Designs & Test of Computers, vol. 8, no. 3, pp. 4957, September 1991, with R. Gupta and R. Srinivasan.
 A systematic approach for designing testable VLSI circuits, Int’l. Conf. on ComputerAided Design (ICCAD), pp. 496499, November 1991, with S.P. Lin and C.A. Njinda.
 Ordering storage elements in a single scan chain, Proc. Int’l. Conf. on ComputerAided Design (ICCAD), pp. 408411, November 1991, with Rajesh Gupta.
 Synthesis of optimal 1hot coded onchip controllers, Int’l. Conf. ComputerAided Design (ICCAD), pp. 236239, November 1991, with D. Mukherjee and C. Njinda.
 Selfdiagnosis of regular arrays of processors, Journal of Computer & Electrical Engineering, vol. 18, no. 2, pp. 159171, 1992, with F. Saheban.
 Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults, IEEE Trans. on ComputerAided Design, vol. 11, no. 5, pp. 659670, May 1992, with K.J. Lee.
 SWiTEST: A switch level test generation system for CMOS combinational circuits, Proc. Design Automation Conf., pp. 26129, June 1992, with K.J. Lee and C.A. Njinda.
 Optimal sequencing of scan registers, Proc. Int’l. Test Conf., pp. 293302, September 1992, with S. Narayanan and C. Njinda.
 SIESTA: A multifacet scan design system, Proc. European Design Automation Conf., pp. 246251, September 1991, with S. Narayanan, C. Njinda and R. Gupta.
 Minimal area merger of finite state machine controllers, Proc. European Design Automation Conf., pp. 278283, September 1992, with D. Mukherjee and M. Pedram.
 A fully integrated CAD environment for designing testable VLSI circuits, Proc. WESCON Technical Conf., pp. 224230, November 1992, with C.A. Njinda and S.L. Lee.
 A partially distributed control scheme for DFT/BIST hardware, Proc. WESCON Technical Conf., pp. 673679, November 1992, with D. Mukherjee and C. Njinda.
 Configurating multiple scan chains for minimum test time, Proc. Int’l. Conf. on Computer Aided Design, pp. 48, November 1992, with S. Narayanan and R. Gupta.
 Testability properties of acyclic structures and applications to partial scan design, Proc. IEEE VLSI Test Symp., pp. 4954, April 1992, with R. Gupta.
 Teaching computer hardware using commercial CAD tools, IEEE Trans. on Education, vol. 36, no. 1, pp. 158163, February 1993, with G. Puvvada.
 Test program synthesis for modules and chips having boundary scan, J. Electronic Testing: Theory and Applications (JETTA), vol. 4, pp. 159180, 1993, with J.C. Lien.
 Generating a family of testable designs using the BILBO methodology, J. Electronic Testing: Theory and Applications (JETTA), vol. 4, pp. 7189, 1993, with S.P. Lin and C.A. Njinda.
 An efficient partitioning strategy for pseudoexhaustive testing, Proc. Design Automation Conf., pp. 242248, June 1993, with R. Srinivasan and S. Gupta.
 Optimal configuration of multiple scan chains, IEEE Trans. on Computers, vol. 42, no. 9, pp. 11211131, September 1993, with S. Narayanan and R. Gupta.
 Novel test pattern generators for pseudoexhaustive testing, Proc. Int’l Test Conf., pp. 10411050, October 1993, with R. Srinivasan and S. Gupta.
 Reconfigurable scan chains: A novel approach to reduce test application time, Proc. Int’l. Conf. on Computer Aided Design (ICCAD), pp. 710715, November 1993, with S. Narayanan.
 Merging multiple FSM controllers for DFT/BIST hardware, Proc. Int’l. Conf. on Computer Aided Design (ICCAD), pp. 720725, November 1993, with D. Mukherjee and M. Pedram.
 Test embedding with discrete logarithms, IEEE VLSI Test Symp., pp. 7480, April 1994, with M. Lempel and S.K. Gupta.
 Extraction of a highlevel structural representation from circuit descriptions with applications to DFT/BIST, Proc. Design Automation Conf., pp. 345350, June 1994, with I. Parulkar and C.A. Njinda.
 A low cost BIST methodology and a novel test pattern generator design, Proc. European Design and Test Conf., pp. 106112, February 1994, with SP. Lin and S.K. Gupta.
 SWiTEST: A switch level test generation system for CMOS combinational circuits, IEEE Trans. on Computer Aided Design, vol. 13 pp. 625637, May 1994, with K.J. Lee and C.A. Njinda.
 Control strategies for chipbased DFT/BIST hardware, Proc. Int’l. Test Conf., pp. 893902, October 1994, with D. Mukherjee and M. Pedram.
 BITS – an integrated CAD system to automate builtin selftest (BIST) of VLSI circuits, Proc. Government Microcircuit Applications Conf. (GOMAC), pp. 4346, Nov. 1994, with SP. Lin.
 Asynchronous multiple scan chains, 13^{th} IEEE VLSI Test Symp., pp. 270276, April 1995, with S. Narayanan.
 Test embedding with discrete logarithms, IEEE Trans. on ComputerAided Design, vol. 14, no. 5, pp. 554586, May 1995, with M. Lempel and S. Gupta.
 Reconfiguration techniques for a single scan chain, IEEE Trans. on Computer Aided Design, vol. 14, no. 6, pp. 750765, June 1995, with S. Narayanan.
 Partial scan design of registertransfer level circuits, J. Electronic Testing: Theory and Applications, vol. 7, no. 1/2, pp. 2546, Aug/Oct 1995, with Rajesh Gupta.
 An integrated system for assigning signal flow directions to CMOS transistors, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp. 14451458, Dec. 1995, with KJ. Lee, CN. Wang and R. Gupta.
 Data path allocation for synthesizing RTL design with low BIST area overhead, Proc. Design Automation Conf., pp. 395401, June 1995, with I. Parulkar and S. Gupta.
 Lower bounds on test resources for scheduling data flow graphs, Proc. Design Automation Conf., pp. 143148, June 1996, with I. Parulkar and S. Gupta.
 Process aggravated noise (PAN): new validation and test problems, Proc. Int’l. Test Conf., pp. 914923, October 1996, with S.K. Gupta.
 High quality robust tests for path delay faults, IEEE VLSI Test Symp., pp. 8893, April 1997, with LC. Chen and S.K. Gupta.
 Analysis of ground bounce in deep submicron circuits, IEEE VLSI Test Symp., pp. 110116, April 1997 with YS. Chang and S.K. Gupta.
 A unified approach for the synthesis of scalable and testable embedded architectures, Proc. 2^{nd} Annual Workshop on FaultTolerant Parallel and Distributed Systems, pp. 3453, April 5, 1997, with P. Bhat, C. Aktouf, V. Prasanna and S. Gupta, and republished in FaultTolerant Parallel and Distributed Systems, ed. D. Avresky and D. Kaeli, Kluwer Academic Publishers, pp. 213220, 1998.
 Fast optimal diagnosis procedures for koutofn systems, IEEE Trans. on Reliability, vol. 46, no. 2, pp. 283290, June 1997, with S. Salloum.
 Analytic models for crosstalk delay and pulse analysis for nonideal inputs, Proc. Int’l. Test Conf., pp. 809818, November 1997, with WY. Chen and S.K. Gupta.
 Introducing redundancy in RTL data paths to reduce BIST resources, Proc. IEEE Int’l. High Level Design Validation and Test Workshop, pp. 5359, Nov. 1415, 1997, with I. Parulkar and S.K. Gupta.
 Scheduling and module assignment for reducing BIST resources, The Design Automation and Test in Europe Conf. 1998, pp. 6673, Feb. 2326, 1998, with I. Parulkar and S.K. Gupta. (Nominated for Best Paper Award)
 Introducing redundant computations in a behavior for reducing BIST resources, Proc. Design Automation Conf., pp. 548553, June 1998, with I. Parulkar and S.K. Gupta.
 Testing a Kary Ncube interconnection network, 4^{th} IEEE Int’l. Online Testing Workshop, pp. 1216, July 1998, Capri, Italy, with S. Kumarasamy and S.K. Gupta.
 Bounds on pseudoexhaustive test lengths, IEEE Trans. on VLSI Systems, vol. 6, no. 3, pp. 420431, September 1998, with R. Srinivasan and S.K. Gupta.
 Allocation techniques for reducing BIST area overhead of data paths, J. Electronic Testing: Theory and Applications (JETTA), vol. 13, no. 2, pp. 149166, Oct. 1998, with I. Parulkar and S.K. Gupta.
 Test generation on VLSI circuits for crosstalk noise, Proc. Int’l. Test Conf., pp. 641650, Nov. 1998, Washington, D.C., with WY. Chen and S.K. Gupta.
 Process variations and their impact on circuit operation, IEEE Int’l. Symp. on Defects and Fault Tolerance in VLSI Systems (DET ’98), pp. 7381, Nov. 24, 1998, Austin, TX, with S. Natarajan and S.K. Gupta.
 An IEEE 1149.1 compliant test control architecture, J. Electronic Testing: Theory and Applications (JETTA), vol. 13, no. 3, pp. 273297, Dec. 1998, with D. Mukherjee.
 Estimation of BIST resources during highlevel synthesis, J. Electronic Testing: Theory and Applications (JETTA), vol. 13, no. 3, pp. 221237, Dec. 1998, with I. Parulkar and S.K. Gupta.
 Test generation for ground bounce in internal logic circuitry, IEEE VLSI Test Symposium, pp. 95104, April 1999, with YS. Chang and S.K. Gupta.
 Test generation for crosstalk induced delay in integrated circuits, Proc. Int’l. Test Conf., pp. 191200, September 1999, with WY. Chen, S.K. Gupta.
 Switchlevel delay test, Proc. Int’l. Test Conf., pp. 171180, September 1999, with S. Natarajan and S.K. Gupta.
 Intelligible testing, Proc. 4^{th} Multimedia Technology and Applications Symp., pp 1119, April 16, 1999, Kaohsuing, Taiwan.
 Intelligible testing in microprocessors, 2^{nd} IEEE Int’l. Workshop on Microprocessor Test and Verification, 11 pages, September 30October 1, 1999, with S.K. Gupta.
 Validation and test generation for oscillatory noise in VLSI interconnects, Proc. Int’l Conf. on ComputerAided Design (ICCAD), pp. 289296, November 1999, with A. Sinha and S.K. Gupta.
 Novel test pattern generators for pseudoexhaustive testing, IEEE Trans. on Computers, vol. 49, no. 11, pp. 12281240, November 2000, with R. Srinivasan and S.K. Gupta.
 Fundamentals of CAD Algorithms, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 14491475, Dec. 2000, with M. Sarrafzadeh and F. Somenzi.
 Test generation for crosstalk induced faults: framework and computational results, Proc. Asian Test Symp. (ATS2000), Taipei, Taiwan, pp. 305310, Dec. 2000, with WY Chen and S.K. Gupta.
 A new framework for static timing analysis, incremental timing refinement, and timing simulation, Proc. Asian Test Symp. (ATS2000), Taipei, Taiwan, pp. 329334, Dec. 2000, with LC Chen and S.K. Gupta.
 Test generation for maximizing ground bounce for internal circuitry with reconvergent fanouts, IEEE Int’l. Test Symp. (VTS), pp. 358366, April/May 2001, with YS Chang and S.K. Gupta.
 A new gate delay model for simultaneous switching and its applications, Proc. Design Automation Conf., pp 289294, June 2001, with LC Chen and S.K. Gupta.
 Validation and test generation for inductance induced noise on VLSI interconnects, Proc. 5^{th} IEEE Workshop on Signal Propagation on Interconnects, May 2001, with A. Sinha and S.K. Gupta.
 Introducing redundant computation in RTL data paths for reducing BIST resources, ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 6., No. 3, pages 423445, July 2001,with I. Parulkar and S. K. Gupta.
 Crosstalk test generation on pseudoindustrial circuits: A case study, Proc. Int’l. Test Conf., pp. 548557, Oct. 30 Nov. 1, 2001, with LC Chen, T. M. Mak, and S. K. Gupta.
 Switchlevel delay test of domino logic circuits, Proc. Int’l. Test Conf., pp. 367376, Oct. 30 Nov. 1, 2001, with S. Natarajan and S.K. Gupta.
 Test generation for crosstalk induced faults: framework and computational results, Asian Test Symp., Taipei, Taiwan, pp. 305310, Dec. 2000, with WY Chen and S.K. Gupta. Republished in 10^{th} Anniversary Compendium of Papers from Asian Test Symposium: 19922001, pp. 311316, Nov. 2001.
 A new framework for static timing analysis, Asian Test Symp., Taipei, Taiwan, pp. 102107, Dec. 2000, with LC Chen and S.K. Gupta. Republished in 10^{th} Anniversary Compendium of Papers from Asian Test Symposium: 19922001, pp. 329334, Nov. 2001.
 Test generation for crosstalkinduced faults: framework and computational results, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, no. 1, pp. 1728, February 2002, with WY Chen and S. K. Gupta.
 TAPSVTiming analysis for partially specified vectors, Journal of Electronic Testing: Theory and Applications, vol. 18, no. 1, pp. 7388, February 2002, with LC Chen and S. K. Gupta.
 Analytical models for crosstalk excitation and propagation in VLSI circuits, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 11171131, October 2002, with WY Chen and S. K. Gupta.
 Validation and test issues related to noise induced by parasitic inductance of VLSI interconnects, IEEE Trans. on Advanced Packaging, vol. 25, no. 3, pp. 329339, August 2002, with A. Sinha and S. K. Gupta.
 Accurate and efficient static timing analysis with crosstalk, Int’l. Conf. on Computer Design (ICCD), pp. 265272, Sept. 2002, with IDe Hwang and S. K. Gupta.
 XIDEN: Crosstalk target identification framework, Proc. Int’l. Test Conf., pp. 365373, October 2002, with S. Nazarian, H. Huang, S. Natarajan, and S. K. Gupta.
 Test generation for maximizing ground bounce considering circuit delay, IEEE VLSI Test Symp., AprilMay 2003, pp. 151157, with YS Chang and S. K. Gupta.
 Analyzing crosstalk in the presence of weak bridge defects, IEEE VLSI Test Symp., AprilMay 2003, pp. 385392, with S. Irajpour, S. Nazarian, L. Wang and S. K. Gupta.
 An enhanced test generator for capacitance induced crosstalk delay faults, Proc. Asian Test Conf., Nov. 2003, pp. 174177, with A. Sinha and S. K. Gupta.
 Estimating error rate in error tolerant VLSI chips, IEEE Int’l. Workshop on Electronic Design, Test and Applications (DELTA), January 2830, 2004, Perth, Australia, pp. 321326.
 Defect and errortolerance in the presence of massive numbers of defects, IEEE Design and Test Magazine, MayJune, 2004, pp. 216227, with S. K. Gupta and T. M. Mak.
 Timingindependent testing of crosstalk in the presence of delay producing defects using surrogate fault models, Proc. Int’l. Test Conf., Oct. 2004, pp. 10241033, with S. Irajpour and S. K. Gupta.
 Intelligible test techniques to support errortolerance, Asian Test Symp., Nov. 2004, pp. 386393.
 Modeling and simulation for crosstalk aggravated by weak bridge defect between onchip interconnects, Asian Test Symp., Nov. 2004, pp. 440447, with L. Wang and S. K. Gupta.
 Efficient identification of crosstalk induced slowdown targets, Asian Test Symp., Nov. 2004, pp. 124131, with S. Nazarian and S. K. Gupta.
 Let’s think analog, Annual Symp. on VLSI, pp. 25, March 2005.
 Multimedia applications and imprecise computation, 8th Euromicro Conf. on Digital System Design, August 30 Sept. 3, 2005, pp. 27.>(This paper was published in conjunction with a keynote address.)
 Multiple tests for each delay fault: higher coverage at lower test application costs, Int’l. Test Conf. (ITC), Paper 47.2, 2005, with S. Irajpour and S. K. Gupta.
 Multiple tests for each delay fault: higher coverage at lower test application costs, TECHCON, with S. Irajpour and S. K. Gupta. Only available online at: http://www.src.org/member/event/E002364/E002364_proceedings.asp.
 A novel testing methodology based on errorrate to support errortolerance, Int’l. Test Conf. (ITC), paper 44.3, 2005, with K. J. Lee and T. Y. Hsieh.
 "STAX: Statistical crosstalk target set compaction," Proc. of Design Automation and Test in Europe, Pages: 172  177, Mar. 2006, with S. Nazarian, M. Pedram and S. K. Gupta.
 An errororiented test methodology to improve yield with errortolerance, VLSI Test Symp., pp. 130–135, April 30May 4, 2006, with TY Hsieh and KJ Lee.
 Diagnosis of delay faults due to resistive bridges, delay variations and defects, Asian Test Symp., pp. 215224, November 2006, with L. Wang and S. K. Gupta.
 Test generation for weak resistive bridges, Asian Test Symp., pp. 265272, November 2006, with S. Irajpour and S. K. Gupta.
 Errortolerance and multimedia, IEEE Int’l. Conf. on Intelligent Information Hiding and Multimedia Signal Processing, pp. 521525, Dec. 1820, 2006, with H. Zhu.
 Reduction of detected acceptable faults for yield improvement via errortolerance, Proc. of Design Automation and Test in Europe (DATE), pp. 15991604, April 2007, with T.Y. Hsieh and K.J. Lee.
 Estimating errorrate in defective logic using signature analysis, IEEE Trans. on Computers, vol. 56, no. 5, pp. 650661, May 2007, with Z. Pan.
 Improving timingindependent testing of crosstalk using realistic assumptions on delay faults, Asian Test Symp., pp. 5764, October 2007, with S. Irajpour and S.K. Gupta.
 Tesla and AND gates, IEEE Design and Test, page 62, Nov.Dec. 2007.
 Preventing overdetection of acceptable faults for yield enhancement, Int’l. J. of Electrical Engineering, Vol. 14, No. 3, pp. 185193, 2007, with T.Y. Hsieh and K.J. Lee.
 An errorrate based test methodology to support errortolerance, IEEE Trans. on Reliability, vol. 57, no. 1, pp. 204214, March 2008, with T.Y. Hsieh and K.J. Lee.
 Error tolerance: Why and how to use slightly defective digital systems, Proc. IEEE Workshop on Silicon Errors in Logic and System Effects, March 2627, 2008, Univ. of Texas, Austin, with K. Chugg, S.K. Gupta and A. Ortega.
 A framework for the analysis of errortolerance, IEEE Design and Test Magazine, vol. 25, no. 2, pp. 168177, March/April 2008, with Haiyang Zhu.
 Basing acceptable errortolerant performance on significancebased errorrate (SBER), IEEE VLSI Test Symp., pp. 5966, April/May 2008, , with Zhaoliang Pan.
 A multivalued algebra for capacitance induced crosstalk delay faults, Asian Test Symp., 2008, pp. 8996, November 2008, with A. Sinha and S.K. Gupta.
 Clarifying the record on testability cost functions, IEEE Design and Test of Computers, vol. 25, no. 6, pp. 607608, November/December 2008.
 An efficient multiphase test technique to perfectly prevent overdetection of acceptable faults for optimal yield improvement via errortolerance, Proc. Int’l. Symp. on VLSI Design, Automation and Test (DAT), April 2730, 2009, Hsinchu, Taiwan, with T.Y. Hsieh and K.J. Lee.
 Tolerance of performance degrading faults for effective yield improvement, Int'l. Test Conf., Lecture paper 3.1, November 2009, with TY Hsieh, M. Annavaram, S.K. Gupta and KuenJong Lee.
 SIRUP: Switch insertion in redundant pipeline structures for yield and yield/area improvement, Asian Test Symp., pp. 193199, November 2009, with M. MirzaAghatabar and S.K. Gupta.
 Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules, Design Automation and Test in Europe (DATE), Dresden, Germany, pp. 812, March 812, 2010, with M. MirzaAghatabar and S.K. Gupta.
 Hardware that produces bounded rather than exact results, Design Automation Conf. (DAC), invited paper, pp. 871876, June 1318, 2010.
 HYPER: a Heuristic for Yield/area imProvEment using Redundancy in SoC, Asian Test Symp., Shanghai, China, pp. 249254, Dec. 14, 2010, with M.M. Aghatabar and S.K. Gupta.
 An errortolerance based test methodology to support product grading for yield enhancement, IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, Vol. 30, No. 6, pp. 930934, June 2011, with T.Y. Hsieh and K.J. Lee.
 Theory of logical partitioning for yield/area maximization using redundancy, IEEE Int’l. Workshop on Design for Manufacturing and Yield (DFM&Y 2011), San Diego, CA, June 6, 2011, with M. M. Aghatabar and S. K. Gupta.
 Yield/area maximization of logic circuits: From theorem to implementation, Int’l. Workshop on Defect and Adaptive Test Analysis (DATA2011), Anaheim CA, Sept. 2223, 2011, with M. M. Aghatabar and S. K. Gupta.
 DACS: Data aware component salvaging in presence of microprocessor integer functional unit delay faults, IEEE Int’l. Workshop on Defect and Adaptive Test Analysis (DATA2011), Anaheim CA, Sept. 2223, 2011, with Y. Gao.
 Theory of Redundancy for Logic Circuits to Maximize Yield/Area, Proc. of the Int’l. Symp. on Quality Electronic Design (ISQED), Santa Clara, CA. March 1921, 2012, with M. M. Aghatabar, S. K. Gupta, and S. Nazarian.
 Efficient overdetection elimination of acceptable faults for yield improvement, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, Vol. 31, No. 5, pp. 754764, May 2012, with T.Y. Hsieh and K.J. Lee.
 Error rate estimation for defective circuits via ones counting, J. ACM Trans. on Design Automation of Electronic Systems, Vol. 27, No. 1, Article #8, January 2012, with Z. Pan.
 A design flow to maximize yield/area of physical devices via redundancy, IEEE Int’t. Test Conf. (ITC), Aneheim, CA, November 68, 2012, with M. M. Aghatabar and S. K. Gupta.
 Using explicit output comparisons for fault tolerant scheduling (FTS) on modern highperformance processors, Design Automation and Test in Europe (DATE), Grenoble, France, pp. 927932, March 1822, 2013, with Y. Gao and S. K. Gupta.
 A new paradigm for trading off yield, area and performance to enhance performance per wafer, Design Automation and Test in Europe (DATE), Grenoble, France, pp. 17531758, March 1822, 2013, with Y. Gao and Y. Wang.
 Trading off area, yield and performance via hybrid redundancy in multicore architectures, IEEE Int’l. Test Symp. (VTS), Berkeley, CA, pp. 16, April 29May 1, 2013, with Y. Gao, Y. Zhang, and D. Cheng.

