Design and Optimization of
Total System Power Constrained Communication Systems
Seminar: EEB248 at 1.30pm on Monday 1 February, 2010
The demand for ever higher performance at lower power is motivating system designers to re-think their design strategies not just in terms of performance, but in terms of joint power-performance efficiency. In this new design paradigm, the performance of a communication system is mainly limited by the “total system power” constraint rather than just the “transmit power”. Therefore, the choice of the optimum data communication algorithm is a strong function of circuit level power-performance trade-offs. Techniques from signal processing can be further applied to devise analysis and characterization techniques that complement system and circuit design. This talk draws examples of the different steps of this type of system level optimization approach from an effort to devise a multi-tone technique, called Analog Multi-Tone (AMT), for high-speed electrical links. Multi Gb/s chip-to-chip links find applications in the data interfaces between microprocessors, memories, peripherals, and network processing components in high performance systems. The talk starts with an overview of AMT signaling and how algorithm design is tailored to the characteristics of high-speed links. We continue by briefly reviewing the development of a mathematical analysis of this system including a convex framework, and closed-form jitter modeling. We then show how Least-Squares based techniques can be applied to define relevant metrics for the characterization a 24-Gb/s prototype AMT transmitter and enable digital compensation of time-variant non-idealities in the 4-way interleaved system. The talk will conclude with a review of other applications and systems that can benefit from this system-level optimization approach.
Amir Amirkhany received the Ph.D. degree from Stanford University in 2007, the M.Sc. degree from the University of California, Los Angeles, in 2002, and the B.Sc. degree from Sharif University of Technology, Tehran, Iran, in 1999, all in Electrical Engineering. He is currently a Senior Member of Technical Staff at Rambus Inc., Los Altos, CA, designing next generation high-speed memory interfaces for graphics applications. Prior to Stanford, he was with Sequoia Communications, working on the ASIC design of WCDMA systems. His main research interests include the design and implementation of communication systems, circuit design, and application of communication and signal processing techniques to the design of low power circuits.
Dr. Amirkhany was a recipient of a Best Student Paper Award at the IEEE Global Communications Conference in 2006 for his work on the design and analysis of an analog multi-tone system for chip-to-chip interconnects. He is the inventor or a co-inventor on more than 10 U.S. and international patent applications in the area of high-speed electrical link.