My current project, funded by NSF, targets very large 3rd or 4th level cache design for high end servers. Shared cache architectures from 100MB to 4GB are evaluated in terms of power and perfomance. This project involves taking bus trace samples on a contemporary multiprocessor and then analizing the samples.
More generally, my interests are in developing and evaluating techniques to improve the behavior of computer systems.
1. Processor microarchitecture
2. Multi-thread, multi-cluster, multi-core chip
3. Cache and memory systems (memory wall)
4. Parallel computer architectures
5. Impact of technology on architecture
6. Power and temperature
7. High-availability and fault tolerance
8. Impact of operating systems on architecture
9. Performance evaluation of real machines
10. Workload analysis and simulation methodology
11. High-end server design for commercial workloads
12. Verification techniques
1. J. Skeppstedt and M. Dubois,"Hybrid prefetching in Multiprocessors," Journal of Parallel and Distributed Computing (JPDC), Vol. 60, No 5, pp.585-615, May 2000.
2. F. Pong and M. Dubois,“A Verification Framework for Delayed Consistency Protocols Based on a Symbolic State Model," IEEE Transactions on Parallel and Distributed Systems, Vol. 11, No. 9, pp. 989-1006, Sept. 2000.
3. M. Dubois, J. Jeong, and A. Nanda,"Shared-Cache Architectures for Decision-Support Systems," International Journal of Performance Evaluation, Vol. 49, September 2002, pp. 283-298.
4. A. Moga and M. Dubois "Scalability Implications of Software-implemented Coherence," International Journal of Computer Systems Scienec & Engineering, Vol. 18, No. 1, Januray 2003, pp. 7-16.
5. Xiagang Qiu and Michel Dubois,"Tolerating Late Memory Traps in Dynamically-scheduled Processors," IEEE Transcations on Computers, June 2004, Vol. 53, No.6, pp.732-743.
6. A. Moga and M. Dubois,"The Impact of Memory Organization in Hybrid DSMs" 2nd Workshop on Software Distributed Shared Memory, Santa Fe, May 2000.
7. X. Qiu and M. Dubois, "Towards Virtually-addressed Memory Hierarchies," Proceedings of the 7th Int. Conf. on High-Performance Computer Architecture (HPCA), January 2001,pp.51-62.
8. J. Jeong, R. Sahoo, K. Sugavanam, A. Nanda, and M. Dubois, "Evaluation of TPC-H Bus Trace Samples Obtained with MemorIES," ISCA 2001 Workshop on Memory Performance Issues, June 2001.
9. M. Kampe, P. Stenstrom, and M. Dubois,"The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches," Proceedings of the 8th Int. Conf. on High-Performance Computer Architecture (HPCA-8), February 2002,pp.223-232.
10. M. Dubois, J. Jeong, S. Jahromi, M. Rouhanizadeh, and A. Nanda,"Evaluation of Shared Cache Architectures for TPC-H.," 5th Workshop on Computer Architecture Evaluation using Commercial Workloads, Cambridge, Mass., Feb 2002, pp. 5-12.
11. J. Jeong and M. Dubois,"Cost-Sensitive Cache Replacement Algorithms," Second Workshop on Caching, Coherence and Consistency, June 2002.
12. M. Dubois, J. Jeong, and A. Nanda,"Shared-Cache Architectures for Decision-Support Systems," Proceedings of Performance 2002, September 2002, pp. 283-298.
13. J. Jeong and M. Dubois, " Cost-sensitive Cache Replacement Algorithms," Proceedings of the Symposium on High-Performance Computer Architecture (HPCA), January 2003.
14. J. Chen, M. Dubois, and P. Stenstrom,"Integrating Complete-System and User-level Performance/Power Simulators: The SimWattch Approach," Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, March 2003.
15. M. Dubois,"Fighting the Memory Wall with Assisted Execution," 2004 ACM Computing Frontiers Conference, April 2004, pp. 168-180.
16. M. Kampe, P. Stenstrom, and M. Dubois,"Self-Correcting LRU Replacement policies," 2004 ACM Computing Frontiers Conference, April 2004, pp. 181-191.
Ph.D. in Electrical Engineering, 1982, Purdue, West Lafayette, IN. Michel Dubois is a Professor in the Department of Electrical Engineering of the University of Southern California. Before joining U.S.C. in 1984, he was a research engineer at the Central Research Laboratory of Thomson-CSF in Orsay, France. His main interests are Computer Architecture and Parallel Processing, with a focus on multiprocessor architecture, performance, and algorithms.
He has published more than 120 technical papers on computer architecture and algorithms(including 39 journal papers). Ten papers were published in the International Symposium on Computer Architecture (ISCA), a premier conference in computer architecture. He has edited two books, one on multiprocessor caches and one on scalable shared memory multiprocessors.
He is well-known in the field of architecture (and well referenced in the literature) for his early contributions (with Christoph Scheurich) to the problem of coherence, synchronization and memory access order in shared-memory multiprocessors.
From 1993 to 2001 he led the RPM Project, a project funded by the National Science Foundation. RPM stands for "Rapid Prototyping engine for Multiprocessors" and is a hardware platform used to implement multiprocessor systems with widely different architectures.
Dubois holds a PhD from Purdue University, an MS from the University of Minnesota, and an engineering degree from the Faculte Polytechnique de Mons in Belgium, all in Electrical Engineering. He is a member of the ACM and an IEEE Fellow.
Department of Electrical Engineering - Systems
Hughes Aircraft Electrical Engineering Building
3740 McClintock Ave.
Los Angeles, CA 90089-2562
Tel: (213) 740-4475
Fax: (213) 740-4418
Research web page