My current project, funded by NSF, targets very large 3rd or 4th level cache design for high end servers. Shared cache architectures from 100MB to 4GB are evaluated in terms of power and perfomance. This project involves taking bus trace samples on a contemporary multiprocessor and then analizing the samples.
More generally, my interests are in developing and evaluating techniques to improve the behavior of computer systems.
1. Processor microarchitecture
2. Multi-thread, multi-cluster, multi-core chip
3. Cache and memory systems (memory wall)
4. Parallel computer architectures
5. Impact of technology on architecture
6. Power and temperature
7. High-availability and fault tolerance
8. Impact of operating systems on architecture
9. Performance evaluation of real machines
10. Workload analysis and simulation methodology
11. High-end server design for commercial workloads
12. Verification techniques
1. J. Skeppstedt and M. Dubois,"Hybrid prefetching in Multiprocessors," Journal of Parallel and Distributed Computing (JPDC), Vol. 60, No 5, pp.585-615, May 2000.
2. F. Pong and M. Dubois,“A Verification Framework for Delayed Consistency Protocols Based on a Symbolic State Model," IEEE Transactions on Parallel and Distributed Systems, Vol. 11, No. 9, pp. 989-1006, Sept. 2000.
3. M. Dubois, J. Jeong, and A. Nanda,"Shared-Cache Architectures for Decision-Support Systems," International Journal of Performance Evaluation, Vol. 49, September 2002, pp. 283-298.
4. A. Moga and M. Dubois "Scalability Implications of Software-implemented Coherence," International Journal of Computer Systems Scienec & Engineering, Vol. 18, No. 1, Januray 2003, pp. 7-16.
5. Xiagang Qiu and Michel Dubois,"Tolerating Late Memory Traps in Dynamically-scheduled Processors," IEEE Transcations on Computers, June 2004, Vol. 53, No.6, pp.732-743.
6. A. Moga and M. Dubois,"The Impact of Memory Organization in Hybrid DSMs" 2nd Workshop on Software Distributed Shared Memory, Santa Fe, May 2000.
7. X. Qiu and M. Dubois, "Towards Virtually-addressed Memory Hierarchies," Proceedings of the 7th Int. Conf. on High-Performance Computer Architecture (HPCA), January 2001,pp.51-62.
8. J. Jeong, R. Sahoo, K. Sugavanam, A. Nanda, and M. Dubois, "Evaluation of TPC-H Bus Trace Samples Obtained with MemorIES," ISCA 2001 Workshop on Memory Performance Issues, June 2001.
9. M. Kampe, P. Stenstrom, and M. Dubois,"The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches," Proceedings of the 8th Int. Conf. on High-Performance Computer Architecture (HPCA-8), February 2002,pp.223-232.
10. M. Dubois, J. Jeong, S. Jahromi, M. Rouhanizadeh, and A. Nanda,"Evaluation of Shared Cache Architectures for TPC-H.," 5th Workshop on Computer Architecture Evaluation using Commercial Workloads, Cambridge, Mass., Feb 2002, pp. 5-12.
11. J. Jeong and M. Dubois,"Cost-Sensitive Cache Replacement Algorithms," Second Workshop on Caching, Coherence and Consistency, June 2002.
12. M. Dubois, J. Jeong, and A. Nanda,"Shared-Cache Architectures for Decision-Support Systems," Proceedings of Performance 2002, September 2002, pp. 283-298.
13. J. Jeong and M. Dubois, " Cost-sensitive Cache Replacement Algorithms," Proceedings of the Symposium on High-Performance Computer Architecture (HPCA), January 2003.
14. J. Chen, M. Dubois, and P. Stenstrom,"Integrating Complete-System and User-level Performance/Power Simulators: The SimWattch Approach," Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, March 2003.
15. M. Dubois,"Fighting the Memory Wall with Assisted Execution," 2004 ACM Computing Frontiers Conference, April 2004, pp. 168-180.
16. M. Kampe, P. Stenstrom, and M. Dubois,"Self-Correcting LRU Replacement policies," 2004 ACM Computing Frontiers Conference, April 2004, pp. 181-191.