Program


  • Sunday, 3 May 2015

  • 17:00 – 18:30    Registration & Reception at S.F.V. Lodge
  • Monday, 4 May 2015      Industrial Workshop

  • 08:00 – 08:45    Registration & Continental breakfast
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  • 08:45 – 09:00    Opening & Welcome   •   Ian W. Jones, Eslam Yahya, Jens Sparsø, and Andreas Steininger    [ Slides ]
  • 09:00 – 10:00    Keynote 1: Bob Iannucci, CMU SV, Toward Platformization for the Internet of Things    [ Slides ]
    • Chair: Ivan Sutherland
  • 10:00 – 10:30    Break
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  • 10:30 – 12:00    Session 1: Clock Domain Crossing
    • Chair: Alex Yakovlev
    • A Pausible Bisynchronous FIFO for GALS Systems    [ Slides ]
      Ben Keller, Matthew Fojtik, and Brucek Khailany
    • How to Synchronize a Pausible Clock to a Reference    [ Slides ]
      Robert Najvirt and Andreas Steininger
    • A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline    (Industrial paper)    [ Slides ]
      L.-C. Trudeau, G. Gagnon, F. Gagnon, C. Thibeault, T. Awad, and D. Morrissey
    • Synchronizers and Data Flip-flops are Different    (Industrial paper)    [ Slides ]
      Jerome Cox, David M. Zar, George Engel, and Ian W. Jones
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  • 12:00 – 13:45    Lunch
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  • 13:45 – 15:15    Session 2: New Circuits, Real Silicon
    • Chair: Andrew Lines
    • Blade – A Timing Violation Resilient Asynchronous Template    [ Slides ]
      Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin Breuer, Ney Laert Vilar Calazans, and Peter A. Beerel
    • Design and Verification of Speed-Independent Multiphase Buck Controller    [ Slides ]
      Danil Sokolov, Victor Khomenko, Andrey Mokhov, Alex Yakovlev, and David Lloyd
    • DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS    [ Slides ]
      Sean Keller, Alain J. Martin, and Chris Moore
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  • 15:15 – 15:45    Break
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  • 15:45 – 17:00    Session 3: Demos
    • Chairs: Arash Saifhashemi and Mehrdad Najibi
    • CAD Tools, Chips, and Posters
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    • Hunting Asynchronous CDC Violations in the Wild    [ Slides ]
      Chris Kwok, Mentor Graphics
    • MetaACE_LTD for Metastability Analysis    [ Slides ]
      David Zar, Blendics
    • Naturalized Communication: Testing Self-Timed Circuits with MrGO    [ Poster ]
      Swetha Mettala Gilla, Marly Roncken, Ivan Sutherland, and Xiaoyu Song, Portland State University
    • Live silicon demo, test, and debug of on-chip network chips, Weaver and Anvil, using MrGO    [ Photo ]
      Navaneeth Jamadagni, Chris Cowan, and Ivan Sutherland, Portland State University
    • Verifying Timing Constraints for Delay-Insensitive Circuits    [ Poster ]
      Hoon Park, Anping He, Marly Roncken, and Xiaoyu Song, Portland State University
    • Low Power design using QDI Asynchronous Technique    [ Poster ]
      Shady Agwa(1), Eslam Yahya(1,2), and Yehea Ismail(1), 1: American University Cairo, 2: Benha University
    • iCrypt – Fully Asynchronous AES Cryptoprocessor    [ Poster ]
      Eslam Yahya(1,2), Nada El-Miligy(1), Moustafa Amin(1), and Yehea Ismail(2), 1: Benha University, 2: American University Cairo

  • Tuesday, 5 May 2015

  • 08:00 – 08:30    Continental breakfast
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  • 08:30 – 10:00    Session 4: Physical Design and Optimization
    • Chair: Steven Nowick
    • Timing Driven Placement for Quasi Delay-Insensitive Circuits    [ Slides ]
      Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, and Rajit Manohar
    • Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation    [ Slides ]
      Gang Wu, Ankur Sharma, and Chris Chu
    • Performance Optimization and Analysis of Blade Designs under Delay Variability    [ Slides ]
      Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin Breuer, Ney Laert Vilar Calazans, and Peter A. Beerel
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  • 10:00 – 10:30    Break
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  • 10:30 – 12:00    Session 5: New Perspectives
    • Chair: Andreas Steininger
    • Analyzing Isochronic Forks with Potential Causality    [ Slides ]    (Best paper award finalist)
      Rajit Manohar and Yoram Moses
    • Naturalized Communication and Testing    [ Slides ]    (Best paper award finalist)
      Marly Roncken, Swetha Mettala Gilla, Hoon Park, Navaneeth Jamadagni, Chris Cowan, and Ivan Sutherland
    • IMAGIN: A Frameless HDR Camera Sensor    (Fresh ideas paper)
      Colin Arnott, Leandra Vicci, and Montek Singh
    • Creating Analog Rudiments Using Self-timed Circuits    (Fresh ideas paper)    [ Slides ]
      Scott Fairbanks
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  • 12:00 – 13:45    Lunch
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  • 13:45 – 15:15    Session 6: Cryptoprocessors and NOCs
    • Chair: Edith Beigné
    • AES Hardware-Software Co-Design in WSN
      Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar
    • Low Power Monolithic 3D IC Design of Asynchronous AES Core    [ Slides ]
      Neela Lohith Penmetsa, Christos Sotiriou, and Sung Kyu Lim
    • Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults    [ Slides ]
      Guangda Zhang, Jim Garside, Wei Song, Javier Navaridas, and Zhiying Wang
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  • 15:15 – 15:45    Break
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  • 15:45 – 16:45    Session 7: Fresh Ideas
    • Chair: Marly Ronken
    • Asynchronous Wake Up Controller for WSN’s Microcontroller: Power Simulation
 and Specifications
      Florent Berthier, Beigné Edith, Pascal Vivet, and Olivier Sentieys
    • A Reconfigurable Device for GALS Systems    [ Slides ]
      Tomohiro Yoneda
    • An Energy Request Scheme for Power Management in Autonomous WSN    [ Slides ]
      Jean-Frédéric Christmann and Edith Beigné
    • Asynchronous Design for Harsh Environments    [ Slides ]
      Jeremy Lopes, Gregory Di Pendina, Edith Beigné, and Lionel Torres
    •  
  • 18:00 – 21:30    Conference Dinner at Ristorante Don Giovanni, 235 Castro Street, Mountain View
    Keynote 2:
    Paul Cunningham and Steev Wilcox, Cadence, A Random Walk from Async to Sync    [ Slides ]
    • Chair: Ian W. Jones

  • Wednesday, 6 May 2015

  • 08:00 – 08:45    Continental breakfast
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  • 08:45 – 09:45    Keynote 3: Ron Ho, Altera, Timing in the Wild: Synchronization, Scale, and FPGAs
    • Chair: Ian W. Jones
  • 09:45 – 10:15    Break
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  • 10:15 – 11:45    Session 8: Merge, Mutual Exclusion, and Arbitration
    • Chair: Tomohiro Yoneda
    • Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters    [ Slides ]    (Best paper award finalist)
      Gabriele Miorandi, Davide Bertozzi, and Steven M. Nowick
    • Opportunistic Merge Element    [ Slides ]
      Andrey Mokhov, Victor Khomenko, Danil Sokolov, and Alex Yakovlev
    • Design and Analysis of Testable Mutual Exclusion Elements    [ Slides ]
      Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Mel Breuer, Ney L. V. Calazans, and Peter A. Beerel
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  • 11:45 – 13:30    Lunch
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  • 13:30 – 14:30    Session 9: Emerging Technologies
    • Chair: Ney Calazans
    • Asynchronous Charge Sharing Power Consistent Montgomery Multiplier    [ Slides ]
      Jiaoyan Chen, Arnaud Tisserand, Emanuel Popovici, and Sorin Cotofana
    • Non-Volatility For Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology    [ Slides ]    (Best paper award winner!)
      E. Zianbetov, E. Beigné, and G. Di Pendina
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  • 14:30 – 15:00    Break & Voting
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  • 15:00 – 16:00    Closing Session
    • Chairs: Andreas Steininger, Ney Calazans, and Ian W. Jones

  • Thursday, 7 May 2015      Social Event

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  • 10:30 – 16:15    Local winery tour & picnic lunch. Sign up
    Please sign up by Wednesday, 29 April
  •  

Keynote 1: Monday, 4 May 2015

iannucci-2013

 

Bob Iannucci

Professor
Carnegie Mellon University
Silicon Valley

 

Toward Platformization for the Internet of Things

 

Abstract

Mobile computing is transforming societies and economies, and the Internet of Things may well become the single largest system the world has ever known, with hundreds of billions of devices connected in ways that, like the Internet, encourage creativity and inspire decades of innovation. For the Internet of Things, we’ve barely started thinking about large-scale systems, how they will be composed, and what we will be able to do with them. We have also only just started thinking about the world’s biggest distributed computing and synchronization problem – writing “apps” for the IoT. We seek the ability to make the devices and networks that we will call the IoT – the IoT platform – accessible to app developers just as has been done with mobile phones. But to do this, we will need to abstract away details of distributed synchronization, timekeeping, and power management across fleets of millions of low-cost, battery-operated, radio-equipped devices. Given these challenges, what form will such an IoT platform take?

In this talk, we will explore some of the important issues relevant to this exciting, if murky, future. Systems-on-chip will be increasingly capable of performing local computation and storage, and the energy cost of these will decline – but the energy cost of communication faces hard limits. Timekeeping across this distributed network impacts the quality of information we can derive from fusing sensor data and it has energy implications for how communication is managed. Networks themselves will play an important role, and dramatic evolution of their architecture and functionality will be essential.

We also present our early work on CROSSMobile – a new type of network that we label cyber-physically enabled to highlight the network’s role in addressing these and other challenges.

Biography

Bob Iannucci is Director of the CyLab Mobility Research Center and a Distinguished Service Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. Previously, he served as Chief Technology Officer of Nokia and Head of Nokia Research Center. Bob’s current research interests include mobile networks, large-scale sensor networks, emergency communications, and indoor positioning systems. He teaches courses in low-power system-on-chip architecture and connected embedded systems architecture. He received his Ph.D. in Electrical Engineering and Computer Science from MIT in 1988.


Keynote 2: Tuesday, 5 May 2015

PAULC_DSC4156_2

Paul Cunningham and Steev Wilcox

 

Paul Cunningham
Vice President of R&D
Cadence Design Systems

 

 

 

Steev Wilcox

Steev Wilcox
Software Engineering Group Director
Cadence Design Systems

 

A Random Walk from Async to Sync

 

 

Abstract

Paul Cunningham and Steev Wilcox tell the story of their journey from Ph.D.’s in asynchronous design to founding an asynchronous design tools startup and then selling their company to Cadence nine years later for technology unrelated to asynchronous design.

Biographies

Paul is Vice President of R&D at Cadence Design Systems where he is responsible for synthesis, design for test, and static verification tools. Paul joined Cadence in 2011 through its acquisition of clock concurrent optimization company Azuro, Inc. where he was co-founder and CEO. He holds a Masters Degree and Ph.D. in Computer Science from the University of Cambridge, England.

Steev is a Software Engineering Group Director at Cadence Design Systems where he is responsible for Clock Concurrent Optimization and Clock Tree Synthesis. He also joined Cadence through the acquisition of Azuro, where he was Chief Architect. He holds a Masters Degree in Mathematics and a Ph.D. in Computer Science from the University of Cambridge, England.


Keynote 3: Wednesday, 6 May 2015

RonHo_Sun_375_563

 

Ron Ho

Architect
Altera Corporation

 

Timing in the Wild: Synchronization, Scale, and FPGAs

 

Abstract

The broader semiconductor industry has moved into the cautious era of post-Moore scalability. No longer can we look to future process nodes with cheaper transistors, and worse yet, our historical “technology entitlement” of transistor performance has evaporated. So how, as an industry, do we continue to envision, plan, and construct compute systems of ever-growing integration and sophistication? One way is to expand our notions of time, data, and energy integration across dies in increasingly complex multi-chip packages; another is to leverage the economic scale of increasingly complex programmable fabrics. At Altera we are pushing on both vectors, and facing challenges not only of designing massive-scale chips in a 14nm FinFET technology, but also of the “timing mode explosion” of user-programmable substrates. In this talk I will review this design context, highlight some of the challenges specific to FPGA timing and synchronization, and discuss some of our methods for coping.

Biography

Ron Ho is currently Architect at Altera, where he leads a team of engineers designing the latest generation of high-performance FPGAs. From 2003 to 2014, Dr. Ho was at Sun Microsystems/Oracle, where he was an Architect (Oracle) and a Distinguished Engineer and Director (Sun). At Sun/Oracle, he worked on a range of technologies spanning capacitive-coupled data transmission, silicon photonics, 3D chip stacking for memory systems, and specialized compute systems for data analytics. From 1993 to 2003, he was with Intel Corporation, where he helped build CPUs ranging from the 486, Pentium II, and Itanium III microprocessors. At times over the past decade he was also Consulting Assistant Professor at Stanford University, where he taught graduate level courses in engineering. Dr. Ho has served on several IEEE conference technical program committees, including ISSCC, A-SSCC, MICRO, VLSI-DAT, Hot- Interconnects, and ASYNC; has been guest editor for the IEEE journals JSSC, TCASII, and JSTQE; and served for four years on the prize jury for the BBVA Foundation Frontiers of Knowledge Awards. He has co-authored over 90 technical conference and journal papers, and has over 50 issued U.S. patents. Dr. Ho is a senior member of the IEEE.