Call for workshop papers

21st IEEE International Symposium on Asynchronous Circuits and Systems

Call for workshop papers - PDF

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4-6 May 2015

Mountain View, Silicon Valley, California, USA

www.asyncsymposium.org

Today a large number of VLSI chips and digital systems designs contain multiple, interacting timing domains. The resulting asynchrony is both an opportunity and a challenge for design, validation, and test. The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in the area of asynchronous design.

Industrial Workshop Papers

ASYNC 2015 will include a special industrial workshop with papers and tutorials from industry and research on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include:

  • Synchronizers and clock domain crossing techniques
  • Techniques for combining asynchronous and clocked designs
  • CAD tools for integrating asynchronous circuits with clocked designs
  • Circuit designs, case studies, comparisons, and applications

We solicit 1-to-2-page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.

A 1-day registration will be offered for the day of this industrial workshop.

“Fresh ideas” Workshop / Tools & Demos

ASYNC 2015 will accommodate a special workshop to present “fresh ideas” in asynchronous design, not yet ready for publication. We solicit 1-to-2-page submissions for the workshop, which will go through a separate light-weight review process. Accepted submissions will be assembled in a binder and handed out at the workshop. We also solicit tools and demos for presentation at the conference.

No revision of submission before publication.

Regular papers

Regular papers in the conference will cover a wide range of asynchronous design topics from design, synthesis, and test, to asynchronous applications in system-level integration and emerging computing technologies. Topics of interest include:

  • Mixed-timed circuits, GALS systems, Network-on-Chip, and multi-chip interconnects
  • Elastic and latency-tolerant synchronous design
  • Asynchronous pipelines, architectures, CPUs, and memories
  • Asynchronous ultra-low power systems, energy harvesting, and mixed-signal/analogue
  • Asynchronous logic in power-constrained applications
  • Asynchronous techniques for 3D integration
  • Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing
  • CAD tools for asynchronous design, synthesis, analysis, and optimization
  • Formal methods for verification and performance/power analysis
  • Test, security, and fault tolerance
  • Asynchronous variability-tolerant design and design for manufacturing
  • Circuit designs, case studies, comparisons, and applications

The accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.

Important Dates

Workshop paper submission deadline 27 Feb 2015
Publication-ready final version due 6 Mar 2015
Industrial paper publication-ready final version due 13 Mar 2015

Industrial Workshop Co-chairs

  • Andrew Lines, Intel Labs,¬†USA
  • Arash Saifhashemi, Intel Labs, USA
  • Mehrdad Najibi, Cadence, USA

Program Chairs

  • Jens Sparso, Technical University of Denmark, Denmark (jspa@dtu.dk)
  • Eslam Yahya, Benha Faculty of Engineering, Benha University CND, American University in Cairo, Zewail City, Egypt (dr.eslam.yahya@gmail.com)

General Chair

  • Ian W. Jones, Oracle Labs, USA (ian.w.jones@oracle.com)

Paper Submission

Papers can be submitted here.