|Speaker||Jeanne Trinko Mechler, IBM Worldwide Design Center|
|Title||Clock Domain Challenges on Networking Chips: A Design Center Perspective|
In order to support the latest communications standards and legacy protocols, today’s networking chips can contain hundreds of clock domains, integrated analog and digital IP, and both synchronous and asynchronous interfaces. Power densities, gigahertz frequencies, switching noise and yield demands have given rise to new clocking complexities. These include power islands, clock gating, clock meshes, performance binning, and logical redundancy. This presentation will explore the clocking challenges on networking chip designs and design techniques applied during layout, clock tree insertion, design for test, power analysis, switching noise analysis, and timing closure.
Jeanne Trinko Mechler, is a distinguished engineer in the IBM worldwide design center. She has 27 years of experience in chip design working in the IBM Systems & Technology Group in Essex Junction, VT. She holds patents and has published papers in the areas of design for test, reliability, failure analysis, and ASIC design. She has completed more than 25 ASIC chip designs, specializing in networking chips containing High Speed SerDes and is the author of the engineering textbook High Speed SerDes Devices and Applications. She received the M.S. and B.S. in electrical engineering from the University of Vermont in 1989 and 1985 respectively, and the M.S. in engineering management from the National Technological University in 1992.