Program

Sunday
5/19/2013
17:00-18:00 On-site Registration
18:00-20:00 Evening Reception: The Garden Terrace at Double Tree Suites
Monday 5/20/2013
08:00-08:40 Registration
08:40-09:00 Opening & Welcome
09:00-10:00 Keynote 1 Andrew Lines
VARIATION-TOLERANT ADAPTIVE AND RESILIENT DESIGN IN NANOSCALE CMOS
Dr. Vivek De, Intel Fellow and Director of Circuit Technology Research, Intel Corporation
10:00-10:30 Break
10:30-12:00 Paper Session 1: Low-Power Design

SOFT MOUSETRAP: A BUNDLED-DATA ASYNCHRONOUS PIPELINE SCHEME TOLERANT TO RANDOM VARIATIONS AT ULTRA-LOW SUPPLY VOLTAGES
Jian Liu, Steven M. Nowick and Mingoo Seok
A LOW-ENERGY VARIATION-TOLERANT ASYNCHRONOUS TCAM FOR NETWORK INTRUSION DETECTION SYSTEMS
Naoya Onizawa, Warren Gross and Takahiro Hanyu
CAPACITOR DISCHARGING THROUGH ASYNCHRONOUS CIRCUIT SWITCHING
Reza Ramezani and Alex Yakovlev
12:00-13:30 Lunch
13:30-14:30 Paper Session: Radiation Hardness Alex Yakovlev
MODULAR REDUNDANCY IN A GALS SYSTEM USING ASYNCHRONOUS RECOVERY LINKS
Jakob Lechner and Varadan Savulimedu Veeravalli
AN SET TOLERANT TREE ARBITER CELL
Syed Rameez Naqvi, Andreas Steininger and Jakob Lechner
14:30-15:00 Break
15:00-16:30 Paper Session 3: Industrial Design and Demos Pascal Viet & Mehrdad Najibi
NANOMESH: AN ASYNCHRONOUS KILO-CORE SYSTEM-ON-CHIP
Jonathan Tse and Andrew Lines
AN ASYNCHRONOUS DATAFLOW SIGNAL PROCESSOR TO MINIMIZE ENERGY PER OPERATION
Bo Marr, Julia Karl, Lloyd Lewins, Kenneth Prager and Dan Thompson
DEMO INTRODUCTIONS
Authors will introduce their software/hardware demo with a one-slide summary.
16:30-17:30 Special Session: Software/Hardware Demo and Reception

Tuesday 5/21/2013
09:00-10:00 Keynote 2 Rajit Manohar
Clock Domain Challenges on Networking Chips: A Design Center Perspective
Jeanne Trinko Mechler, Distinguished Engineer, IBM Worldwide Design Center
10:00-10:30 Break
10:30-12:00 Paper Session 4: Analysis and Automation
CELLTK: AUTOMATED LAYOUT FOR ASYNCHRONOUS CIRCUITS WITH NONSTANDARD CELLS
Robert Karmazin, Carlos Tadeo Ortega Ortero and Rajit Manohar
STATISTICAL STATIC TIMING ANALYSIS OF CONDITIONAL ASYNCHRONOUS CIRCUITS USING MODEL-BASED SIMULATION
Eslam Yahya, Laurent Fesquet, Yehea Ismail and Marc Renaudin
DERIVING PERFORMANCE BOUNDS FOR CONDITIONAL ASYNCHRONOUS CIRCUITS USING LINEAR PROGRAMING
Mehrdad Najibi and Peter A. Beerel
12:00-13:30 Lunch
13:30-15:00 Paper Session 5: GALS and Randomness
OPTIMAL GALS DESIGN FOR SPECTRAL PEAK ATTENUATION ON DIGITAL SWITCHING CURRENT
Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dähnert, Milos Krstic and Eckhard Grass
DISTRIBUTED PHASE CORRECTION TECHNIQUE
Suwen Yang and Frankie Liu
A SELF-TIMED RING BASED TRUE RANDOM NUMBER GENERATOR
Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert and Laurent Fesquet
15:00-15:30 Break
15:30-17:00 Paper Session 6: Asynchronous Communication and Networks
SAS: SOURCE ASYNCHRONOUS SIGNALING PROTOCOL FOR ASYNCHRONOUS HANDSHAKE COMMUNICATION FREE FROM WIRE DELAY OVERHEAD
Shomit Das, Vikas Vij and Kenneth Stevens
CLASSIFYING VIRTUAL CHANNEL ACCESS CONTROL SCHEMES FOR ASYNCHRONOUS NOCS
Robert Najvirt, Syed Rameez Naqvi and Andreas Steininger
A BIT OF ANALYSIS ON SELF-TIMED SINGLE-BIT ON-CHIP LINKS
Jonathan Tse, Benjamin Hill and Rajit Manohar
17:00-18:00 Break (on your own)
18:00-20:00 Reception and Banquet: Casa del Mar, Hotel by the Sea

Wednesday 5/22/2013
09:00-10:00 Special Session: Asynchronous Venture Updates
Three start-ups talk about their latest asynchronous chips

10:00-10:30 Break
10:30-12:00 Paper Session 7: QDI Design and Verification
CAN QDI COMBINATIONAL CIRCUITS BE IMPLEMENTED WITHOUT C-ELEMENTS?
Fu-Chiung Cheng and Chi Chen
AUTOMATIC LEAKAGE CONTROL FOR WIDE RANGE PERFORMANCE QDI ASYNCHRONOUS CIRCUITS IN FD-SOI TECHNOLOGY
Jeremie Hamon and Edith Beigne
INVERTING MARTIN SYNTHESIS FOR VERIFICATION
Stephen Longfield and Rajit Manohar
12:00-13:30 Lunch
13:30-15:00 Paper Session 8: Synchronization and Crossing Clock Boundaries
MTBF BOUNDS FOR MULTISTAGE SYNCHRONIZERS
Salomon Beer, David Zar, Jerome Cox and Tom Chaney
MTBF ESTIMATION IN COHERENT CLOCK DOMAINS
Salomon Beer, Ran Ginosar and Yoav Weizman
AN APPROACH FOR EFFICIENT METASTABILITY CHARACTERIZATION OF FPGAS THROUGH THE DESIGNER
Thomas Polzer and Andreas Steininger
15:30-15:30 Break
15:30-16:30 Paper Session 9: Formal Methods
FORMAL DEADLOCK VERIFICATION FOR CLICK CIRCUITS
Freek Verbeek, Sebastiaan Joosten and Julien Schmaltz
UNFAITHFUL GLITCH PROPAGATION IN EXISTING BINARY CIRCUIT MODELS
Matthias Függer, Thomas Nowak and Ulrich Schmid
16:30-17:00 Break
17:00-17:30 Best Paper Award and Closing