Attendees are invited to attend the following demos to be held during the ASYNC 2013 Symposium, which will take place May 19-22, 2013 in Santa Monica, California.
The demo session, scheduled on Monday, May 20th in the afternoon, enables both academic researchers and industrial companies to exhibit their recent work in the area of asynchronous design. This year demos include demonstrations of CAD tools, simulation environments, integrated circuit designs, and FPGA prototypes as follows.
|An event driven and ultra-low power asynchronous processor|
|Demonstrators:||Carlos Tadeo Ortega Otero, Rajit Manohar|
|Cornell University, Computer Systems Laboratory|
|In this demo, we show a fully implemented state-of-the-art ultra-low power event driven microcontroller, suitable for applications that require high performance under bursty workloads. This deeply embedded microcontroller was designed to be a self-contained and self-powered system that delivers enough performance for the demands current mobile applications require.
Our QDI design and event driven architecture make the core of the microcontroller run at fast cycle times while retaining the lowest possible power envelope. Our microcontroller is in the energy-performance Pareto optimal set, when compared to other processors in its class. Our 90nm test chip can adjust to multiple applications by running at 93MIPS in high-performance mode or using only 29 pJ in low-energy mode while still delivering 45MIPS.
Our event driven processor is part of the efforts of the Asynchronous VLSI and Architecture group at Cornell to investigate energy efficient architectures and ultra-low power architectures for sensor networks.
Asynchronous FPGA fabricated using cellTK automated layout flow
|Cornell University, Computer Systems Laboratory|
|We will demonstrate a recent quasi delay-insensitive asynchronous FGPA prototype. It has a dataflow-driven architecture with fine-grained pipelining designed to support high throughput.
Physical design was performed using cellTK, an automated layout tool developed at Cornell (also presented at ASYNC 2013). The FPGA was fabricated in 130nm technology as a split-manufacturing demonstration vehicle. In this technique, a (possibly untrusted) foundry performs Front-End-of-Line transistor fabrication while a second, trusted foundry manufactures the Back-End-of-Line wiring. This allows access to cutting edge FEOL technology while limiting exposure to piracy or malicious alteration.
We will also demonstrate our development board and software programming toolflow. In addition to asynchronous dataflow graphs, standard synchronous designs can also be mapped to the FPGA. The chip was designed to allow for easy testing, and includes a default configuration for process characterization and frequency taps for performance measurement.
|MetaACE: A Simulation Tool for the Study of Metastability in SoCs|
|Demonstrator:||David M. Zar|
|Senior Engineer Blendics, Inc|
|MetaACE is the first commercial product able to simulate synchronizer failure events due to metastability issues. MetaACE is unique in its ability to predict circuit behavior across all variations of process parameters, supply voltages, operating temperatures and the increasingly important effects of circuit aging. Using MetaACE, the digital system designer is able to identify circuits at risk of synchronizer failures by estimating their mean time between failures (MTBF). The analysis of the circuit is done through simulation, allowing the designer to mitigate any problems before fabrication of the integrated circuit.
We will demonstrate MetaACE running on sample circuits and demonstrate how easy it is to use the tool as well as what happens as parameters are changed (such as Vdd, temperature, process corner, etc.). We welcome discussion on how the tool works and why metastability should be a concern to designers working in the smaller geometries.
Energy-Modulated Computing: First Samples of Self-Powered Life on a Die
|Demonstrators:||Reza Ramezani, Maxim Rykunov, Abdullah Baz, Xuefu Zhang, Delong Shang, Andrey Mokhov, Danil Sokolov, Fei Xia and Alex Yakovlev|
|Microelectronics Systems Design Group, School of EEE, Newcastle University|
|This demo will illustrate the principle of energy-modulated computing according to which the flow of energy entering a computing system determines its computational flow. This principle will be fundamental for building future autonomous systems, such as those powered by energy harvesting sources and aimed for survival in power-deficient conditions. The demo includes a set of experimental circuits (with three VLSI chips and PCBs) to work in variable power supply conditions, including:
(i) A reference-free voltage sensor based on self-timed charge-to-digital converter (180nm chip),
(ii) A fully speed-independent SRAM providing data retention down to very low Vdd level, and operating in run-time varying Vdd (90nm chip);
(iii) A self-timed 8051 microcontroller that dynamically adjusts its operation to power levels; it was semi-automatically synthesized using our own model “Conditional Partial Order Graphs” (130nm chip)
(iv) A switched-capacitor power converter for asynchronous loads (PCB version).
|Modular Redundancy in a GALS System using Asynchronous Recovery Links|
|Vienna University of Technology|
|In this demonstration we will show an FPGA prototype of a fault-tolerant GALS system, designed following the methods presented in the paper “Modular Redundancy in a GALS System using Asynchronous Recovery Links” of this year’s ASYNC symposium. System-critical GALS modules are replicated and perform state exchange and subsequent voting on regular basis to recover from faults.
The showcase for our demonstration will feature a small GALS system performing AES decryption of an incoming data stream. The GALS circuits are replicated among three FPGA boards to form a TMR system. We will show that the system is able to recover from transient faults within one of the replicas by manipulating the circuit state using hardware fault injection. As an extension to the results of our paper, we will also demonstrate that the system is able to cope with permanent defects in a single replica and can re-integrate a hot-swapped replacement unit.