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EE 457X
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EE 457x: Computer Systems Organization
This is supplemental course information, designed to give you a fuller picture of the course and an expanded look at the topics covered. This is an unofficial document. The USC Course Catalog is the binding description of all university courses. Information such as books, materials covered, and the order of topics is subject to change. Please consult instructor for this semseter to get more upto date course information.
Catalog Data:
EE 457x Computer Systems Organization (3, FaSpSm)
Register transfer level machine organization; MPIS instruction set architecture; performance; computer arithmetic; organization and detailed implementation of non-pipelined and pipelined processors; cache and virtual memory.
Not available for graduate credit to computer science majors.
Prerequisite: EE 357.
Text book:
Primary References:
- Class Notes and Lab Manual (required): Please buy from the university (USC) bookstore. Remote students can call (213) 740-TEXT and place a phone order.
- Textbook: "Computer Organization & Design - The Hardware and Software Interface" 3rd edition Revised Printing By D. A. Patterson (Berkeley) and J.L. Hennesy (Stanford)
Please buy from the university (USC) bookstore or any place (such as online bookstores). The book has a companion website. If you have second edition of the textbook, or the 3rd edition but not the revised printing, that is fine too.
Secondary References:
- EE101 and EE201L Textbook: Digital Design Principles and Practices By John F. Wakerly
- EE357 Textbook: Computer Organization by Hamacher
- Advanced Computer Architecture with Parallel Programming By Kai Hwang
- Computer Architecture - A Quantitative Approach By D. A. Patterson and J. L. Hennessy
- Computer Arithmetic Algorithms By Israel Koren
Course monitors:
Gandhi Puvvada
Topics:
- Review of essentials from EE102L and EE357
- Computer performance
- Instructions
- Arithmetic
- The processor
- Pipelining
- Memory Systems
- Additional Computer Arithmetic Handout (classnotes)
Fast adders, Multipliers, Non-linear pipelines
- Parallel Processors
Course Objectives:
- To provide students with a substantial understanding of
- a CPU at its logic design level through the design of the control unit and the data path unit of a simple multi-clock-cycle CPU and a pipelined CPU.
- computer arithmetic, cache and virtual memories
- To expose students to the benefits of digital logic simulation tools through extensive design and simulation lab exercises.
Course Outcomes:
The students will be able to:
- design a simple CPU at logic level.
- understand the pipelining concepts and related issues.
- evaluate coding sequences with execution time (thereby performance) in mind.
- design simple arithmetic unit
- perform design entry, simulation, and functional verification using CAD tools
- understand the datapath and the control associated with a cache memory implementation and a virtual memory implementation
- proceed to graduate courses in computer architecture
- appreciate the relation between the low-level hardware of a CPU and compilers/operating systems written for that CPU.
Laboratory Projects:
- Max. Min. finder State Machine Design Lab #1 Part #1 and #2
- Lab #2 (cancelled)
- Design of a 32-bit ALU Lab #3
- Design of a combinational divider
- Multi-cycle CPU Design Lab #4 Part #1, #2, #3 and #4
- Pipelined Ripple Carry Adder Design Lab #5
- Design of a Pipelined CPU (Revised in Fall 2006) Lab #6 Part #1, #2, #3, and #4
- Design of a 3-element adder Lab #7 Part #1, #2, #3
Last Updated: 11/19/2007
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