This
is supplemental course information, designed to give you a fuller
picture of the course and an expanded look at the topics covered. This
is an unofficial document. The USC Course Catalog is the binding
description of all university courses. Information such as books,
materials covered, and the order of topics is subject to change. Please
consult instructor for this semseter to get more upto date course
information.
Catalog Data:
Linear passive circuits; pulse and digital circuits, timing; MOS and CMOS
FETs; interface circuits, standards; transmission line theory of pulses;
problems of high speed circuits. Not available for credit to electrical
engineering majors. Prerequisite: EE 326Lx (Essentials of Electrical Engineering).
Note:
This course is currently under revision in both content and format.
Textbook:
CMOS Digital Integrated Circuits, Kang and Leblebici, McGraw-Hill, 1999.
CMOS IC Layout, Clein, Newnes, 2000
Coordinator:
Edward W. Maby, Senior Lecturer
Topics:
1. MOSFET structure and characteristic terminal relations.
2. Basic analysis and design techniques pertaining to static and dynamic
behavior of RTL, nMOS, and CMOS inverters.
3. Circuit models for signal propagation in VLSI systems, and design/layout
techniques for delay minimization.
4. Analysis and design of semiconductor memory circuits.
5. Clock circuits, and design techniques for effective clock distribution.
Course Objectives:
To introduce students to devices, processes, and design techniques used
to implement digital circuits in very-large-scale integrated systems.
Course Outcomes:
The student will be able to:
1. Describe the MOSFET structure and the basic relevant fabrication processes.
2. Analyze simple n- or p-channel MOSFET circuits that operate in the
cutoff, resistive, or saturation modes (including the body effect, when
applicable).
3. Design an “RTL”, nMOS, or CMOS inverter, given specific
features of the input-output transfer characteristic.
4. Perform a layout of a CMOS inverter subject to process design rules,
and extract capacitance values that limit dynamic performance.
5. Use PSpice to verify the static and dynamic behavior of device-level
digital circuits.
6. Model and analyze VLSI interconnect circuits that limit signal propagation
times.
7. Design ROM, sRAM, and dRAM memory cells that exhibit specific READ
and WRITE electrical functionality.
8. Design simple clock circuits and implement elementary layout techniques
that promote minimum clock skew.
9. Perform and interpret laboratory measurements to determine MOSFET electrical
parameters and inverter performance characteristics.
10. Design, layout, and evaluate a VLSI standard cell (as in the comprehensive
project).
Laboratory Projects:
Performed as a component of the “studio” instructional format.
Prepared by: Edward W. Maby Date: 8 April 2002
