Logo: University of Southern California

Course Software - Cadence

  

University of Southern California
Cadence University Program Member
This page contains information related to Cadence Tools used in courses at USC

Teaching
 
Cadence tools are actively being used in the following courses.
 
477L MOS VLSI Circuit Design: Analysis and design of digital MOS VLSI circuits including area, delay and power minimization. Laboratory assignments including design, layout, extraction, simulation and automatic synthesis.
 
536ab Mixed-Signal Integrated Circuit Design a: MOSFET operation and models; voltage references and biasing; elementary amplifier configurations; design techniques for high-speed operational amplifiers, comparators and transconductors; compensation methods. b: Non-linear integrated circuits, data-converter architectures and implementations, comprehensive design project.
 
552 Asynchronous VLSA Design: Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
 
577ab VLSI System Design: Integrated circuit fabrication; circuit simulation; basic device physics; simple device layout; structured chip design; timing; project chip; MOS logic; system design silicon compilers. b: VLSI design project; preparation of chips for fabrication; testing fabricated chips; design examples; design of specific units (e.g., buses); design techniques; testability; system integration.

632 Integrated Communication Systems: Analysis and design of high-speed integrated communication systems at circuit and system levels. Emphasis on broadband wireless applications. Transceiver architectures, amplifiers, oscillators, frequency synthesizers.

Disclaimer
 
Information is provided "as is" without warranty or guarantee of any kind.  No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk — and any attempt to use this information is at your own risk — we recommend using it on a copy of your data to be sure you understand what it does and under your conditions.  Keep your master intact until you are personally satisfied with the use of this information within your environment."
 
This site is maintained by EE Webmaster and was last updated on 10/13/2014.
 
"Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134."